The software is written in C and running on the VxWorks real-time OS… Lockheed Martin (who wrote the control systems) switched from ADA to C a few years back. There are plenty more interesting details in the article. Here are a few teasers:

The RAD 6000 has built in error detection and corrections. So the hardware does RAM scrubbing. There is a RAM scrubbing that occurs on a continuous basis. And beyond that, we have internal fault protection that monitors the health and safety of the software. And if a software task, for example, fails to respond to a ping, we have pings in the system, then the fault protection task will declare that a fault has occurred and will safe the spacecraft. And what that means, by “safeing”, we mean that the spacecraft will enter into a power and communications safe mode where it will just sit and wait for the ground to respond. It’ll basically phone home and say, I’ve got a problem; somebody tell me what to do.

So if it were to completely lock-up, the hardware has to be stroked every 64 seconds. There’s a watch-stop timer. And so if that 64 second period expires, then the hardware resets and the software is rebooted, and hopefully that clears whatever error occurred. Now in the event that that doesn’t work, we have a whole second set of avionics onboard. So the hardware will try to boot to the same side, and if the same side doesn’t come up and start stroking the watch-stop timer, then it will swap to the other side and boot the first side.

Interviewer: Am I right in assuming that there’s very little process separation in the older RAD 6000 boards?

Peter: Exactly… We have strict coding guidelines that we use. We don’t allow dynamic memory allocation, for example.

These are true fail-safe systems… not the stuff we mortal engineers play with. Click HERE to read the rest of the interview.

Anyways, a few months ago, Intel made this music video promoting the technology:

(requires Adobe Flash plugin… click HERE to watch it on YouTube)

Perks like Google’s appeal to integrators, people for whom work life and home life have little distinction. These are the employees who like to plug into the wi-fi system on Google’s commuter bus and do work as they ride to and from the office; who check office e-mail frequently at home on nights and weekends; and who like child-care facilities at or near their office so that they can bring a part of home with them to work.

Segmentors, by contrast, like to maintain distinct walls between work and home. These are people made uncomfortable by a workplace filled with perks related to one’s personal life. Even employees with children can dislike the fact that their employer provides on-site childcare.

I also found this interesting:

In her research, Rothbard documented how segmentors in an integrationist workplace enjoyed less job satisfaction and had a lower commitment to their companies than their integrator co-workers. What was noteworthy, too, was that segmentors may not know the reasons they are dissatisfied at work. “It’s a subtle effect, where they know they just don’t fit in but may not know why,” Rothbard says.

I tend to be a segmentor… I enjoy my private life separate from work. This could explain why I never quite felt at home working at Intel, which is highly “integrationist”…

Read the full article here

Click here to watch the video (requires Flash Player)

If you listen close, he even mentions the Folsom Chipset group I used to work for

Edited 1-30-2007:

The exciting thing about the new 45nm process is that Intel is replacing the SiO₂ (silicon-dioxide) gate dielectric with a high-k dielectric like HfO₂ (hafnium-dioxide). The gate dielectric is a thin layer (about 5 atoms thick with SiO₂) that prevents current from leaking through the gate.

The problem is that the electric field generated by the gate must still be strong enough to create the inversion channel between the source and drain of the transistor (more information here). As transistors get smaller, the dielectric layer has to be so thin (to maintain the correct capacitance) that current begins to flow (leak) across the gate dielectric. This consumes power and generates heat.

By switching to a high-k dielectric, the gate layer can be thicker without increasing its overall capacitance. This is significant, because the transistor can be made smaller while still having a relatively think gate layer. The thinker gate layer means less current leakage across the dielectric, which translates into lower power consumption and thus less heat per transistor.

In summary, all of this means transistors can be made smaller AND more efficient. As transistors get smaller, they switch faster, which means increased CPU performance. Also, since the new transistors are more efficient, more of them can be crammed into a single area without generating too much heat. Moore’s law just keeps on ticking…

Here’s an actual picture of a transistor in a modern CPU (90nm process) taken using an electron microscope:

The gate is 50nm across (shown in white behind the “50nm” label). The gate dielectric is the thin layer between the gate and the dark substrate below it.

As a side note: a nanometer is about 10,000 times SMALLER than the width of a human hair.