Tour of Intel’s new 45nm fab

On January 29, 2007, in Tech and Security, by Tom

Here’s a 40-minute video of Intel Senior Fellow, Mark Bohr, giving Robert Scoble a tour of Intel’s new 45nm chip fabrication plant. Most of the interview focuses on the 45nm technology, but there are several shots inside the fab.

Click here to watch the video (requires Flash Player)

If you listen close, he even mentions the Folsom Chipset group I used to work for :-)

Edited 1-30-2007:

The exciting thing about the new 45nm process is that Intel is replacing the SiO2 (silicon-dioxide) gate dielectric with a high-k dielectric like HfO2 (hafnium-dioxide). The gate dielectric is a thin layer (about 5 atoms thick with SiO2) that prevents current from leaking through the gate.

SiO2 layer closeup

The problem is that the electric field generated by the gate must still be strong enough to create the inversion channel between the source and drain of the transistor (more information here). As transistors get smaller, the dielectric layer has to be so thin (to maintain the correct capacitance) that current begins to flow (leak) across the gate dielectric. This consumes power and generates heat.

By switching to a high-k dielectric, the gate layer can be thicker without increasing its overall capacitance. This is significant, because the transistor can be made smaller while still having a relatively think gate layer. The thinker gate layer means less current leakage across the dielectric, which translates into lower power consumption and thus less heat per transistor.

In summary, all of this means transistors can be made smaller AND more efficient. As transistors get smaller, they switch faster, which means increased CPU performance. Also, since the new transistors are more efficient, more of them can be crammed into a single area without generating too much heat. Moore’s law just keeps on ticking…

Here’s an actual picture of a transistor in a modern CPU (90nm process) taken using an electron microscope:

90nm Gate Closeup

The gate is 50nm across (shown in white behind the “50nm” label). The gate dielectric is the thin layer between the gate and the dark substrate below it.

As a side note: a nanometer is about 10,000 times SMALLER than the width of a human hair.

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